Has anyone encountered this error before. My entire project is in Systemverilog.
6. Executing SLANG frontend.
src/chip_core.sv:18:17: error: direction 'InOut' on inlined port connection unsupported
inout wire VDD,
^
src/chip_core.sv:19:17: error: direction 'InOut' on inlined port connection unsupported
inout wire VSS,
^
src/chip_core.sv:38:39: error: direction 'InOut' on inlined port connection unsupported
inout wire [NUM_ANALOG_PADS-1:0] analog // Analog
2